IIT Bombay, set up by an Act of Parliament, was established in 1958, at Powai, a northern suburb of Mumbai. Today the Institute is recognised as one of the centres of academic excellence in the country. Over the years, there has been dynamic progress at IIT Bombay in all academic and research activities, and a parallel improvement in facilities and infrastructure, to keep it on par with the best institutions in the world. Institutes in positions of excellence grow with time. The ideas and ideals on which such institutes are built evolve and change with national aspirations, national perspectives, and trends world - wide. IIT Bombay, too, is one such institution.

Department Of Electrical Engineering

The EE department at IIT Bombay has been active in teaching and research since its inception in 1957. Currently, about 45 faculty members are engaged in research in the areas of Communication and Signal Processing, Control and Computing, Power Electronics and Power Systems, Microelectronics and VLSI design, and Electronic Systems.
The department has academic programmes with about 320 undergraduate and 200 postgraduate students. The department is equipped with the latest experimental and computational facilities for taking up R & D and consultancy activities in various fields.

CTARA

Since its inception in 1985, Center for Technology Alternatives for Rural Areas (CTARA) at IIT-Bombay is involved in design and development of technologies relevant to rural areas. The current working areas of CTARA include farm machinery, food processing, low cost housing, renewable energy, water management, rural industry etc. The CTARA carries out its programmes through full time research assistants, visiting experts and associated faculty members from different disciplines at IIT. Presently the undergraduate and graduate students from other engineering or applied science disciplines participate in CTARA activities as a part of thesis or project requirement.

CONTENTS

1. Introduction

2. Cooling Using Microchannels

3. Two Phase Flow in Microchannels

4. Annular Flow Model

5. Fabrication of Silicon Chip

6. Lithography

7. Photolithography

8. Lithography Module

9. Etching

10.Conclusion

11.Scope for Future work

12.References

1. INTRODUCTION

Power densities encountered in microelectronic equipment have increased tremendously due to progress in semiconductor technology. Integrated circuits in the near future are expected to have such large power densities, that traditional air cooling will no longer be sufficient to cool them. The thermal design goal is to limit the magnitude of chip temperature rise above ambient temperature in order to ensure satisfactory electrical circuit operation and reliability. For optimal performance and lifetime of these devices, more efficient cooling techniques will be required.

Microprocessors, in the near future, are expected to have a requirement for removing a very large amount of heat from a small area. Conventional air cooled heat sinks will no longer be sufficient to cater to this requirement. Heat transfer to fluids flowing through microchannels is being looked upon as a promising solution to this problem. Hence, a thorough understanding of heat transfer in microchannels has become a necessity.

Our knowledge of macro-scale heat transfer cannot in general be directly applied to heat transfer in microchannels. Experimentation and modeling studies are being carried out by various researchers around the world to obtain a better understand of micro-scale heat transfer. There is a need for the development of better models and correlations to explain experimental observations related to microflows. Annular flow is a flow pattern observed by several researchers in microchannels. Annular flow model has been studied, modified and extended for obtaining the pressure distribution and for handling non-uniform heating along the microchannel.

Figure 3.1 is a representation of the annular flow in a microchannel.

Figure Error! No text of specified style in document.. 1 (a) Schematic of annular flow pattern in a microchannel heat sink [8]

(b) Idealized annular flow region [8]

The model has been constructed by means of equations for mass conservation and momentum conservation in the liquid film and the vapor core. These mass and momentum conservation equations have been solved numerically and the predictions have been compared with experimental data. Good agreement has been claimed between experimental data and model predictions.

Dryout

When there is a very high heat input into the channel, the fluid film may completely evaporate. This condition is known as dryout. The annular flow equations are no longer valid beyond this point. Hence, appropriate changes must be incorporated in the program to identify this scenario.

5. FABRICATION OF SILICON CHIP

Channels are made with glass and silicon using microfabrication techniques. Channel masks are printed in positive with a high-resolution printer on transparent paper for lithography. Photoresist is spin coated on a silicon wafer. The wafer is then exposed to UV light through the mask. Channels are etched at different depths using Deep Reactive Ion Etching (DRIE). The sealing is made with Pyrex glass using anodic bonding, providing optical access for flow analysis.

Two-phase flow microchannel module

mixing section

Properly introducing gas bubbles is an important step in producing a two-phase flow pattern. We micromachined an effective small mixing section on-chip. Well-defined bubbles in a wide range of sizes can be produced as a function of liquid and gas flow rates. Because of the square channel symmetries, bubbles flow “naturally” in the center of the channel. The cross-shaped was chosen to produce a steady uniform flow. The minimal size of bubbles is about the size of the channel. In these experiments, this mixing system is used as an effective way to produce two-phase flows in microdevices.

6. LITHOGRAPHY

Lithography is typically the transfer of a pattern to photosensitive material by selective exposure to a radiation source such as light. A photosensitive material is a material that experiences in its physical properties when exposed to a radiation source. If we selectively expose a photosensitive material to radiation (e.g. by masking some of the radiation) the pattern of the radiation on the material is transferred to the material exposed, as the properties of the exposed and unexposed regions differ (as shown in fig 1).

litho_fig1

Figure 1: Transfer of pattern to a photosensitive material

This discussion will focus on optical lithography, which is simply lithography using a radiation source with wavelength(s) in the visible spectrum.

In lithography for micromachining, the photosensitive material used is typically a photoresist (also called resist, other photosensitive polymers are also used). When resist is exposed to a radiation source of a specific a wavelength, the chemical resistance of the resist to developer solution changes. If the resist is placed in a developer solution after selective exposure to a light source, it will etch away one of the two regions (exposed or unexposed). If the exposed material is etched away by the developer and the unexposed region is resilient, the material is considered to be a positive resist (shown in figure 2a). If the exposed material is resilient to the developer and the unexposed region is etched away, it is considered to be a negative resist (shown in figure 2b).

litho_fig2

Figure 2: a) Pattern definition in positive resist, b) Pattern definition in negative resist.

Lithography is the principal mechanism for pattern definition in micromachining. Photosensitive compounds are primarily organic, and do not encompass the spectrum of materials properties of interest to micro-machinists. However, as the technique is capable of producing fine features in an economic fashion, a photosensitive layer is often used as a temporary mask when etching an underlying layer, so that the pattern may be transferred to the underlying layer (shown in figure 3a). Photoresist may also be used as a template for patterning material deposited after lithography (shown in figure 3b). The resist is subsequently etched away, and the material deposited on the resist is "lifted off".

The deposition template (lift-off) approach for transferring a pattern from resist to another layer is less common than using the resist pattern as an etch mask. The reason for this is that resist is incompatible with most MEMS deposition processes, usually because it cannot withstand high temperatures and may act as a source of contamination

litho_fig3

Figure 3: a) Pattern transfer from patterned photoresist to underlying layer by etching, b) Pattern transfer from patterned photoresist to overlying layer by lift-off.

Once the pattern has been transferred to another layer, the resist is usually stripped. This is often necessary as the resist may be incompatible with further micromachining steps. It also makes the topography more dramatic, which may hamper further lithography steps.

Alignment

In order to make useful devices the patterns for different lithography steps that belong to a single structure must be aligned to one another. The first pattern transferred to a wafer usually includes a set of alignment marks, which are high precision features that are used as the reference when positioning subsequent patterns, to the first pattern (as shown in figure 4). Often alignment marks are included in other patterns, as the original alignment marks may be obliterated as processing progresses. It is important for each alignment mark on the wafer to be labeled so it may be identified, and for each pattern to specify the alignment mark (and the location thereof) to which it should be aligned. By providing the location of the alignment mark it is easy for the operator to locate the correct feature in a short time. Each pattern layer should have an alignment feature so that it may be registered to the rest of the layers.

litho_fig4

Figure 4: Use of alignment marks to register subsequent layers

Depending on the lithography equipment used, the feature on the mask used for registration of the mask may be transferred to the wafer (as shown in figure 5). In this case, it may be important to locate the alignment marks such that they don't effect subsequent wafer processing or device performance. For example, the alignment mark shown in figure 6 will cease to exist after a through the wafer DRIE etch. Pattern transfer of the mask alignment features to the wafer may obliterate the alignment features on the wafer. In this case the alignment marks should be designed to minimize this effect, or alternately there should be multiple copies of the alignment marks on the wafer, so there will be alignment marks remaining for other masks to be registered to.

litho_fig5

Figure 5: Transfer of mask registration feature to substrate during lithography (contact aligner)

litho_fig6

Figure 6: Poor alignment mark design for a DRIE through the wafer etch (cross hair is released and lost).

Alignment marks may not necessarily be arbitrarily located on the wafer, as the equipment used to perform alignment may have limited travel and therefore only be able to align to features located within a certain region on the wafer (as shown in figure 7). The region location geometry and size may also vary with the type of alignment, so the lithographic equipment and type of alignment to be used should be considered before locating alignment marks. Typically two alignment marks are used to align the mask and wafer, one alignment mark is sufficient to align the mask and wafer in x and y, but it requires two marks (preferably spaced far apart) to correct for fine offset in rotation.

litho_fig7

Figure 7: Restriction of location of alignment marks based on equipment used.

As there is no pattern on the wafer for the first pattern to align to, the first pattern is typically aligned to the primary wafer flat (as shown in figure 8). Depending on the lithography equipment used, this may be done automatically, or by manual alignment to an explicit wafer registration feature on the mask.

litho_fig8

Figure 8: Mask alignment to the wafer flat.

7. PHOTOLITHOGRAPHY

Photolithography or optical lithography is a process used in semiconductor device fabrication to transfer a pattern from a photomask (also called reticle) to the surface of a substrate. Often crystalline silicon in the form of a wafer is used as a choice of substrate, although there are several other options including, but not limited to, glass, sapphire, and metal. Photolithography (also referred to as "microlithography" or "nanolithography") bears a similarity to the conventional lithography used in printing and shares some of the fundamental principles of photographic processes.

Photolithography involves a combination of:

substrate preparation
photoresist application
soft-baking
exposure
developing
hard-baking
etching

and various other chemical treatments (thinning agents, edge-bead removal etc.) in repeated steps on an initially flat substrate.

A part of a typical silicon lithography procedure would begin by depositing a layer of conductive metal several nanometers thick on the substrate. A layer of photoresist -- a chemical that hardens when exposed to light (often ultraviolet) -- is applied on top of the metal layer. The photoresist is selectively "hardened" by illuminating it in specific places. For this purpose a transparent plate with patterns printed on it, called a photomask or shadowmask, is used together with an illumination source to shine light on specific parts of the photoresist. Some photoresists work well under broadband ultraviolet light, whereas others are designed to be sensitive at specific frequencies to ultraviolet light. It is also possible to use other types of resist that are sensitive to X-Rays and others that are sensitive to electron-beam exposure.

A spinner used to apply photoresist to the surface of a silicon wafer.

Generally most types of photoresist will be available as either "positive" or "negative". With positive resists the area that you can see (masked) on the photomask is the area that you will see upon developing of the photoresist. With negative resists it is the inverse, so any area that is exposed will remain, whilst any areas that are not exposed will be developed. After developing, the resist is usually hard-baked before subjecting to a chemical etching stage which will remove the metal underneath.

Finally, the hardened photoresist is etched using a different chemical treatment, and all that remains is a layer of metal in the same shape as the mask (or the inverse if negative resist has been used).

Lithography is used because it affords exact control over the shape and size of the objects it creates, and because it can create patterns over an entire surface simultaneously. Its main disadvantages are that it requires a substrate to start with, it is not very effective at creating shapes that are not flat, and it can require extremely clean operating condition.

8. The LITHOGRAPHY MODULE

Typically lithography is performed as part of a well-characterized module, which includes the wafer surface preparation, photoresist deposition, alignment of the mask and wafer, exposure, develop and appropriate resist conditioning. The lithography process steps need to be characterized as a sequence in order to ensure that the remaining resist at the end of the modules is an optimal image of the mask, and has the desired sidewall profile.

The standard steps found in a lithography module are (in sequence): dehydration bake, HMDS prime, resist spin/spray, soft bake, alignment, exposure, post exposure bake, develop hard bake and descum. Not all lithography modules will contain all the process steps. A brief explanation of the process steps is included for completeness.

· Dehydration bake - dehydrate the wafer to aid resist adhesion.

· HMDS prime - coating of wafer surface with adhesion promoter. Not necessary for all surfaces.

· Resist spin/spray - coating of the wafer with resist either by spinning or spraying. Typically desire a uniform coat.

· Soft bake - drive off some of the solvent in the resist, may result in a significant loss of mass of resist (and thickness). Makes resist more viscous.

· Alignment - align pattern on mask to features on wafers.

· Exposure - projection of mask image on resist to cause selective chemical property change.

· Post exposure bake - baking of resist to drive off further solvent content. Makes resist more resistant to etchants (other than developer).

· Develop - selective removal of resist after exposure (exposed resist if resist is positive, unexposed resist if resist is positive). Usually a wet process (although dry processes exist).

· Hard bake - drive off most of the remaining solvent from the resist.

· Descum - removal of thin layer of resist scum that may occlude open regions in pattern, helps to open up corners

9. ETCHING

Etching is a method of printmaking in which the image is incised into the surface of a metal plate using an acid.

Wet etching is the removal of material by immersing the wafer in a liquid bath of chemical etchant. There are two kinds of wet etching etchants, isotropic etchants and anisotropic etchants:

Isotropic etchants attack the material being etched at the same rate in all directions.
Anisotropic etchants attack the silicon wafer at different rates in different directions. On wafers the most used etchant is KOH.

Anisotropic etching does not cause undercutting, and is preferred in applications where straight side walls are essential.

Anisotropic etching requires a substrate with a well defined crystalline structure such as silicon. The etch is directional and proceeds along the exposed plane in the crystal lattice. As atoms are removed from the crystal lattice, different planes are exposed to the etchant. Since the density of atoms on the planes varies, the etch rate varies significantly.

wet etch

Figure 1: Difference between anisotropic and isotropic wet etching.

In silicon, a popular anisotropic wet etch substrate, the initial (0 degree) surface is called 100 and etches a hundred times faster than the 110 (45 degree) and 111 (54 degree) surfaces. This results in a consistent wedge shaped etch pattern.

Wet etching is also used for the characterization of the quality of a wafer. The etch pit density is a measure for the number of dislocations per area.

10. CONCLUSIONS

Two phase heat transfer to fluids flowing through microchannels is a promising solution to the problem of cooling integrated circuits with very high power densities. Macro-scale results cannot be directly applied to microchannels. Onset of annular flow and dryout may be significantly affected by the location of a hotspot along the microchannel. In a practical cooling device having a set of parallel microchannels with common inlet and exit manifolds, the flow will distribute itself between the channels depending on the heat input to each of the channels. In certain cases, it is not possible to have equal pressures across two channels without encountering dryout in one of them.

Parametric studies may help an engineer to choose suitable operating conditions for microchannel heat sink. These studies are also helpful in understanding the physics involved in two phase flows. Hydraulic diameter of the microchannel, mass flow rate,

Heat input and subcooling at the inlet are some of the parameters that can affect the pressure drop across the microchannels and two phase heat transfer coefficient.

11. SCOPE FOR FUTURE WORK

There is a great scope for doing experimental work to verify the predictions of

these modeling studies. The results presented in the chapter on parametric studies may prove to be especially suitable for experimental verification. There is scope for including more features in the annular flow model, like a temperature dependent viscosity, to possibly obtain a better match with experimental observations. Based on the modeling and experimental results, some standards could be developed for the design of microchannel heat sinks to be used for cooling microprocessors

12. REFERENCES

[1] G. Hetsroni, Z. Mosyak, G. Ziskind, A uniform temperature heat sink for cooling of electronic devices, Int. J. Heat Mass Transfer 45 (2002) 3275-3286.

[2] L. Zhang, J. Koo, L.Jiang, M. Ashegi, K. Goodson, J. Santiago, T. Kenny, Measurement and modeling of two-phase flow in microchannels with nearly constant heat flux boundary condition, J. Microelectromech. Syst. 11 (2002) 12-19.

[3] W. Qu, I. Mudawar, Flow boiling heat transfer in two-phase microchannel heat sinks—I. Experimental investigation and assessment of correlation methods, Int. J. Heat Mass Transfer 46 (2003) 2755-2771.

[4] P. Lee, H. Li, F. Tseng, C. Pan, Nucleate boiling Heat transfer in Silicon-based microchannels, Proceedings of ASME summer heat transfer conference, 2003, pp.1-4.

[5] W. Qu, I. Mudawar, Flow boiling heat transfer in two-phase microchannel heat sinks—II. Annular two-phase flow model, Int. J. Heat Mass Transfer 46 (2003) 2773-2784.

[6] S. Kandalikar, Microchannels and Minichannels - History, terminology, classification and current research needs, Proceedings of First International Conference on Microchannels and Minichannels, 2003, pp. 1-6.

Engineering the engineers™

Practical Training Report at IIT Mumbai

2. COOLING USING MICROCHANNELS

3. TWO PHASE FLOW IN MICROCHANNELS

4. ANNULAR FLOW MODEL

Dryout

11. SCOPE FOR FUTURE WORK

12. REFERENCES